1. Field of the Invention
The present invention relates to a method to fabricate interconnect structures that are part of integrated circuits and microelectronic devices by utilization of irradiation to remove and clean a sacrificial material used therein. The primary advantages of this method are reduced damage to interlayer dielectric layers that result in higher reliability and improved performance through reductions in moisture uptake and resistance-capacitance delays, respectively.
2. Background Art
It is widely known that the speed of propagation of interconnect signals is one of the most important factors controlling overall circuit speed as feature sizes are reduced and the number of devices per unit area is increased. Throughout the semiconductor industry, there has been a strong drive to reduce the dielectric constant, k, of the interlayer dielectric materials existing between metal lines. As a result, interconnect signals travel faster through conductors due to a reduction in resistance-capacitance (RC) delays. Unfortunately, these strategies are difficult to implement due to numerous issues associated with processing and integrating low dielectric constant materials as these materials can be especially prone to damage by various processes employed in the generation of interconnect structures. The damage observed in the dielectric materials is manifested by an increase in the dielectric constant and increased moisture uptake which may result in reduced performance and device reliability.
To reduce the dielectric constant of interlayer dielectric materials, a common approach is to introduce porosity into the material. This approach effectively supplants a portion of the dielectric material with air which has a dielectric constant of unity. Unfortunately, the introduction of porosity results in materials that are substantially more prone to modification by various processes commonly employed in the fabrication of interconnect structures as the porosity in these materials can often provide a pathway by which various chemical components can easily access the bulk of the low-k material. Thus, unlike dense dielectric systems, whereby modification may be localized to the surface of the dielectric and consequently may result in only minor effects, the extent of modification for a porous material can be dramatic as these changes can be realized through the entire dielectric material.
One particular processing step that is known to damage porous interlayer dielectric materials, including dielectric materials comprised of Si, C, O, and H, are plasma strip processes (i.e., dry strip) that are often used to remove sacrificial materials that are required in the integration process. These processes can result in removal of carbon in the interlayer dielectric film and may occur by a mechanism which involves de-methylation and often results in increase dielectric constants and hydrophilicity of the materials. To minimize the damage associated with such processes, efforts have been placed in developing improved processes that result in less damage to the interlayer dielectrics or developing new materials that are less prone to damage. Although some progress has been made, the damage associated with plasma strip and related processes remain as a key issue in the integration/implementation of low-k dielectric materials for advanced interconnect structures.
Alternatively, wet strip processes are also being explored to supplant damaging dry strip processes; however, these processes may also result in damage to the interlayer dielectric. Furthermore, these processes often cause logistic issue (such as switching from a dry etch tool to a wet tool) and result in the creation of waste products as the wet clean used for these processes cannot be used indefinitely.
Finally, there have been approaches to address the issue of damage by subsequent repair processes that utilize a chemical component that reacts with the modified low-k interlayer dielectric. These approaches may involve silylating agents that convert pendent silanol groups to a different functional group resulting in a recovery of the hydrophobicity (i.e., reduced moisture uptake) of the dielectric and reduction of the dielectric constant from its damaged state. Although, these approaches may be promising, the additional processing step required for damage recovery may result in additional processing costs, material wastes, and lower yields.
Thus, in order to achieve high performance microelectronic devices, it is necessary to reduce the dielectric constant of the interlayer dielectric materials to reduce resistance-capacitance (RC) delays. The use of low-k materials as interlayer dielectrics provides the reduction in capacitance between conducting metal features; however, these materials must be processed in a manner such that their attributes are not significantly degraded resulting in higher dielectric constants or moisture uptake which will invariably lead to reduced performance and/or reliability. Unfortunately, these low-k materials are prone to damage by various processes utilized in common integration schemes including dry strip processes. Consequently, alternative approaches to minimize or eliminate the processes that are sources for damage are important.